The purpose of this application is to provide an educational tool for the development and understanding of high-level circuit logic diagrams and their hardware virtualization in the VHDL language.

The system will allow for circuit logic diagrams to be generated from VHDL primitives (AND, OR, and NOT gates, etc.). Circuit logic may also be implemented using 'black box' components, which have underlying logic encoded in VHDL generated dynamically or user-specified. This functionality will be achieved via a drag-and-drop graphical user interface.

There will also be an interface for the dynamic creation of high-level components such as multiplexors and n-bit arithmetic logic units. Users may specify the number of inputs and outputs for such components, whose underlying logic will be developed algorithmically via plug-ins to the system.