{VERSION 6 0 "IBM INTEL NT" "6.0" } {USTYLETAB {CSTYLE "Maple Input" -1 0 "Courier" 0 1 255 0 0 1 0 1 0 0 1 0 0 0 0 1 }{CSTYLE "2D Math" -1 2 "Times" 0 1 0 0 0 0 0 0 2 0 0 0 0 0 0 1 }{CSTYLE "2D Output" 2 20 "" 0 1 0 0 255 1 0 0 0 0 0 0 0 0 0 1 } {PSTYLE "Normal" -1 0 1 {CSTYLE "" -1 -1 "Times" 1 12 0 0 0 1 2 2 2 2 2 2 1 1 1 1 }1 1 0 0 0 0 1 0 1 0 2 2 0 1 }{PSTYLE "Text Output" -1 6 1 {CSTYLE "" -1 -1 "Courier" 1 10 0 0 255 1 2 2 2 2 2 1 2 1 3 1 }1 1 0 0 0 0 1 0 1 0 2 2 0 1 }{PSTYLE "Maple Output" -1 11 1 {CSTYLE "" -1 -1 "Times" 1 12 0 0 0 1 2 2 2 2 2 2 1 1 1 1 }3 3 0 0 0 0 1 0 1 0 2 2 0 1 }{PSTYLE "Maple Output" -1 12 1 {CSTYLE "" -1 -1 "Times" 1 12 0 0 0 1 2 2 2 2 2 2 1 1 1 1 }1 3 0 0 0 0 1 0 1 0 2 2 0 1 }{PSTYLE "Title" -1 18 1 {CSTYLE "" -1 -1 "Times" 1 18 0 0 0 1 2 1 1 2 2 2 1 1 1 1 }3 1 0 0 12 12 1 0 1 0 2 2 19 1 }{PSTYLE "Author" -1 19 1 {CSTYLE "" -1 -1 "Times" 1 12 0 0 0 1 2 2 2 2 2 2 1 1 1 1 }3 1 0 0 8 8 1 0 1 0 2 2 0 1 }{PSTYLE "Normal" -1 256 1 {CSTYLE "" -1 -1 "Times" 1 18 0 0 0 1 2 2 2 2 2 2 1 1 1 1 }3 1 0 0 0 0 1 0 1 0 2 2 0 1 }} {SECT 0 {PARA 18 "" 0 "" {TEXT -1 24 "A Simple Cache Simulator" }} {PARA 19 "" 0 "" {TEXT -1 14 "Jeremy Johnson" }}{PARA 0 "" 0 "" {TEXT -1 0 "" }}{PARA 0 "" 0 "" {TEXT -1 428 "This worksheet provides a simp le cache simulator, which takes three cache design parameters [size, a ssociativity, and block size] and a sequence of addresses and returns \+ the number of cache misses. The simulator only simulates a single lev el unified cache [the address sequence does not distinguish reads, wri tes or instructions vs. data]. The least recently used (lru) strategy is used when a cache line needs to be replaced." }}{PARA 0 "" 0 "" {TEXT -1 0 "" }}{PARA 0 "" 0 "" {TEXT -1 448 "Create a data structure \+ for the Cache simulator. An array, indexed by the cache index and set , is returned. Each entry in the array stores the tag and a clock tic k, which is used to keep track of the time [index into the address lis t that is passed to the simulator] that the element is accessed. A ze ro entry in the clock field indicates that the cache entry is invalid. The clock information is used to implement the lru replacement strat egy." }}{PARA 0 "" 0 "" {TEXT -1 0 "" }}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 20 "Cache := proc(C,A,B)" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 27 " local i, j, cache, slots;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 21 " slots := C/(B*A); " }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 36 " cach e := array(0..slots-1,0..A-1);" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 28 " \+ for i from 0 to slots-1 do" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 26 " \+ for j from 0 to A-1 do" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 43 " cac he[i,j] := table([tag=0,clock=0]);" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 7 " od;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 5 " od;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 21 " return eval(cache);" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 4 "end;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 2 " " }}{PARA 12 "" 1 "" {XPPMATH 20 "6#>%&CacheGf*6%%\"CG%\"AG%\"BG6&%\"iG%\"jG%&ca cheG%&slotsG6\"F/C&>8'*(9$\"\"\"9&!\"\"9%F7>8&-%&arrayG6$;\"\"!,&F2F5F 5F7;F?,&F8F5F5F7?(8$F?F5F@%%trueG?(8%F?F5FBFE>&F:6$FDFG-%&tableG6#7$/% $tagGF?/%&clockGF?O-%%evalG6#F:F/F/F/" }}}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 22 "cache := Cache(8,1,1);" }}{PARA 12 "" 1 "" {XPPMATH 20 "6#>%&cacheGK%&ARRAYG6$7$;\"\"!\"\"(;F*F*7*/6$F*F*K%&TABLEG6#7$/%&c lockGF*/%$tagGF*Q(pprint26\"/6$\"\"\"F*KF1F2Q(pprint6F9/6$\"\"#F*KF1F2 Q(pprint7F9/6$\"\"$F*KF1F2Q(pprint5F9/6$\"\"%F*KF1F2Q(pprint0F9/6$\"\" &F*KF1F2Q(pprint1F9/6$\"\"'F*KF1F2Q(pprint4F9/6$F+F*KF1F2Q(pprint3F9Q( pprint8F9" }}}{EXCHG {PARA 0 "" 0 "" {TEXT -1 36 "CacheSim implements \+ the simulator. " }}}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 17 "# Cache Simulator" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 9 "# Inputs:" }}{PARA 0 " > " 0 "" {MPLTEXT 1 0 30 "# addr : a list of addresses" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 21 "# C : Cache size" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 24 "# A : Associativity" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 21 "# B : Block size" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 86 "# TRACE : boolean flag. If TRACE is true, each address in th e trace is printed along" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 79 "# \+ with a message indicating whether the cache access was a hit or no t." }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 9 "# Output:" }}{PARA 0 "> " 0 " " {MPLTEXT 1 0 88 "# misses : the number of cache misses that would o ccur using the specified cache design" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 54 "# on the given sequence of addresses. " }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 34 "CacheSim := proc(addr,C,A,B,TRACE)" }} {PARA 0 "> " 0 "" {MPLTEXT 1 0 82 " local cache, slots, i, j, n, bloc k, offset, index, found, rep, minclock, misses;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 57 " cache := Cache(C,A,B); slots := C/(A*B); misses : = 0;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 73 " printf(\"Cache size = %d, Associativity = %d, Block size = %d\\n\",C,A,B);" }}{PARA 0 "> " 0 " " {MPLTEXT 1 0 41 " printf(\"Number of slots = %d\\n\",slots);" }} {PARA 0 "> " 0 "" {MPLTEXT 1 0 18 " n := nops(addr);" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 24 " for i from 1 to n do " }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 56 " block := floor(addr[i]/B); offset := addr[i] mod B;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 46 " index := block mod slots ; found := false;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 75 " if TRACE \+ then printf(\"%d-th address = %d -> %d\\n\",i,addr[i],index); fi;" }} {PARA 0 "> " 0 "" {MPLTEXT 1 0 26 " for j from 0 to A-1 do" }} {PARA 0 "> " 0 "" {MPLTEXT 1 0 71 " if block = cache[index,j][tag ] and cache[index,j][clock] > 0 then" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 54 " found := true; cache[index,j][clock] := i; " }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 43 " if TRACE then printf(\"hit\\n\") ; fi;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 9 " fi;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 7 " od;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 21 " \+ if not found then" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 41 " if TRAC E then printf(\"miss\\n\"); fi;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 46 " misses := misses + 1; minclock := n+1; " }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 35 " for j from 0 to A-1 do " }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 50 " if cache[index,j][clock] < minclock then " }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 55 " minclock := cache[i ndex,j][clock]; rep := j;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 11 " \+ fi;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 9 " od;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 37 " cache[index,rep][tag] := block;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 35 " cache[index,rep][clock] := i;" }} {PARA 0 "> " 0 "" {MPLTEXT 1 0 7 " fi;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 5 " od;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 16 " return m isses;" }}{PARA 0 "> " 0 "" {MPLTEXT 1 0 4 "end;" }}{PARA 12 "" 1 "" {XPPMATH 20 "6#>%)CacheSimGf*6'%%addrG%\"CG%\"AG%\"BG%&TRACEG6.%&cache G%&slotsG%\"iG%\"jG%\"nG%&blockG%'offsetG%&indexG%&foundG%$repG%)mincl ockG%'missesG6\"F9C*>8$-%&CacheG6%9%9&9'>8%*(F@\"\"\"FA!\"\"FBFG>8/\" \"!-%'printfG6&QVCache~size~=~%d,~Associativity~=~%d,~Block~size~=~%d| +F9F@FAFB-FL6$Q6Number~of~slots~=~%d|+F9FD>8(-%%nopsG6#9$?(8&FFFFFS%%t rueGC)>8)-%&floorG6#*&&FW6#FYFFFBFG>8*-%$modG6$F\\oFB>8+-Fao6$FgnFD>8, %&falseG@$9(-FL6&Q:%d-th~address~=~%d~->~%d|+F9FYF\\oFdo?(8'FJFF,&FAFF FFFGFZ@$3/Fgn&&F<6$FdoF`p6#%$tagG2FJ&Ffp6#%&clockGC%>FhoFZ>F[qFY@$F[p- FL6#Q%hit|+F9@$4FhoC(@$F[p-FL6#Q&miss|+F9>FI,&FIFFFFFF>8.,&FSFFFFFF?(F `pFJFFFapFZ@$2F[qF_rC$>F_rF[q>8-F`p>&&F<6$FdoFgrFhpFgn>&FjrF\\qFYOFIF9 F9F9" }}}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 169 "T1 := [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 2, 4, 6, 8, 10, 12, 14, \+ 0, 4, 8, 12, 2, 6, 10, 14, 1, 3, 5, 7, 9, 11, 13, 15, 1, 5, 9, 13, 3, \+ 7, 11, 15];" }}{PARA 11 "" 1 "" {XPPMATH 20 "6#>%#T1G7R\"\"!\"\"\"\"\" #\"\"$\"\"%\"\"&\"\"'\"\"(\"\")\"\"*\"#5\"#6\"#7\"#8\"#9\"#:F&F(F*F,F. F0F2F4F&F*F.F2F(F,F0F4F'F)F+F-F/F1F3F5F'F+F/F3F)F-F1F5" }}}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 9 "nops(T1);" }}{PARA 11 "" 1 "" {XPPMATH 20 "6#\"#[" }}}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 25 "Cach eSim(T1,8,1,1,false);" }}{PARA 6 "" 1 "" {TEXT -1 49 "Cache size = 8, \+ Associativity = 1, Block size = 1" }}{PARA 6 "" 1 "" {TEXT -1 19 "Numb er of slots = 8" }}{PARA 11 "" 1 "" {XPPMATH 20 "6#\"#[" }}}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 25 "CacheSim(T1,8,1,2,false);" }}{PARA 6 "" 1 "" {TEXT -1 49 "Cache size = 8, Associativity = 1, Block size = 2" }}{PARA 6 "" 1 "" {TEXT -1 19 "Number of slots = 4" }}{PARA 11 "" 1 "" {XPPMATH 20 "6#\"#S" }}}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 25 "CacheSim(T1,8,2,1,false);" }}{PARA 6 "" 1 "" {TEXT -1 49 "Cache size \+ = 8, Associativity = 2, Block size = 1" }}{PARA 6 "" 1 "" {TEXT -1 19 "Number of slots = 4" }}{PARA 11 "" 1 "" {XPPMATH 20 "6#\"#[" }}} {EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 169 "T2 := [0, 1, 2, 3, 4, 5, 6, 7, 0, 4, 1, 5, 2, 6, 3, 7, 8, 9, 10, 11, 12, 13, 14, 15, 8, 12, 9, 13 , 10, 14, 11, 15, 0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15 ];" }}{PARA 11 "" 1 "" {XPPMATH 20 "6#>%#T2G7R\"\"!\"\"\"\"\"#\"\"$\" \"%\"\"&\"\"'\"\"(F&F*F'F+F(F,F)F-\"\")\"\"*\"#5\"#6\"#7\"#8\"#9\"#:F. F2F/F3F0F4F1F5F&F.F'F/F(F0F)F1F*F2F+F3F,F4F-F5" }}}{EXCHG {PARA 0 "> \+ " 0 "" {MPLTEXT 1 0 25 "CacheSim(T2,8,1,1,false);" }}{PARA 6 "" 1 "" {TEXT -1 49 "Cache size = 8, Associativity = 1, Block size = 1" }} {PARA 6 "" 1 "" {TEXT -1 19 "Number of slots = 8" }}{PARA 11 "" 1 "" {XPPMATH 20 "6#\"#K" }}}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 25 "Cach eSim(T2,8,1,2,false);" }}{PARA 6 "" 1 "" {TEXT -1 49 "Cache size = 8, \+ Associativity = 1, Block size = 2" }}{PARA 6 "" 1 "" {TEXT -1 19 "Numb er of slots = 4" }}{PARA 11 "" 1 "" {XPPMATH 20 "6#\"#C" }}}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 24 "CacheSim(T2,8,2,1,true);" }}{PARA 6 "" 1 "" {TEXT -1 49 "Cache size = 8, Associativity = 2, Block size = 1" }}{PARA 6 "" 1 "" {TEXT -1 19 "Number of slots = 4" }}{PARA 6 "" 1 "" {TEXT -1 21 "1-th address = 0 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 21 "2-th address = 1 -> 1" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 21 "3-th addres s = 2 -> 2" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 21 "4-th address = 3 -> 3" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss " }}{PARA 6 "" 1 "" {TEXT -1 21 "5-th address = 4 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 21 "6-th address = 5 -> 1" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 21 "7-th address = 6 -> 2" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }} {PARA 6 "" 1 "" {TEXT -1 21 "8-th address = 7 -> 3" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 21 "9-th address = 0 -> 0 " }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 "" {TEXT -1 22 "10 -th address = 4 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 "" {TEXT -1 22 "11-th address = 1 -> 1" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 "" {TEXT -1 22 "12-th address = 5 -> 1" }} {PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 "" {TEXT -1 22 "13-th \+ address = 2 -> 2" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 " " {TEXT -1 22 "14-th address = 6 -> 2" }}{PARA 6 "" 1 "" {TEXT -1 3 "h it" }}{PARA 6 "" 1 "" {TEXT -1 22 "15-th address = 3 -> 3" }}{PARA 6 " " 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 "" {TEXT -1 22 "16-th address = 7 -> 3" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 "" {TEXT -1 22 "17-th address = 8 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }} {PARA 6 "" 1 "" {TEXT -1 22 "18-th address = 9 -> 1" }}{PARA 6 "" 1 " " {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 23 "19-th address = 10 \+ -> 2" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 23 "20-th address = 11 -> 3" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }} {PARA 6 "" 1 "" {TEXT -1 23 "21-th address = 12 -> 0" }}{PARA 6 "" 1 " " {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 23 "22-th address = 13 \+ -> 1" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 23 "23-th address = 14 -> 2" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }} {PARA 6 "" 1 "" {TEXT -1 23 "24-th address = 15 -> 3" }}{PARA 6 "" 1 " " {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 22 "25-th address = 8 - > 0" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 "" {TEXT -1 23 "26-th address = 12 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 "" {TEXT -1 22 "27-th address = 9 -> 1" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 "" {TEXT -1 23 "28-th address = 13 -> \+ 1" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 "" {TEXT -1 23 "2 9-th address = 10 -> 2" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 " " 1 "" {TEXT -1 23 "30-th address = 14 -> 2" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 "" {TEXT -1 23 "31-th address = 11 -> 3" }} {PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 "" {TEXT -1 23 "32-th \+ address = 15 -> 3" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 "" 1 " " {TEXT -1 22 "33-th address = 0 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 4 "m iss" }}{PARA 6 "" 1 "" {TEXT -1 22 "34-th address = 8 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 22 "35-th address = 1 -> 1" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 22 "36-th address = 9 -> 1" }}{PARA 6 "" 1 "" {TEXT -1 4 "mis s" }}{PARA 6 "" 1 "" {TEXT -1 22 "37-th address = 2 -> 2" }}{PARA 6 " " 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 23 "38-th address \+ = 10 -> 2" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 22 "39-th address = 3 -> 3" }}{PARA 6 "" 1 "" {TEXT -1 4 "mis s" }}{PARA 6 "" 1 "" {TEXT -1 23 "40-th address = 11 -> 3" }}{PARA 6 " " 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 22 "41-th address \+ = 4 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 23 "42-th address = 12 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }} {PARA 6 "" 1 "" {TEXT -1 22 "43-th address = 5 -> 1" }}{PARA 6 "" 1 " " {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 23 "44-th address = 13 \+ -> 1" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 22 "45-th address = 6 -> 2" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }} {PARA 6 "" 1 "" {TEXT -1 23 "46-th address = 14 -> 2" }}{PARA 6 "" 1 " " {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 22 "47-th address = 7 - > 3" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 23 "48-th address = 15 -> 3" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }} {PARA 11 "" 1 "" {XPPMATH 20 "6#\"#K" }}}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 16 "T3 := [0,8,0,8];" }}{PARA 11 "" 1 "" {XPPMATH 20 "6#> %#T3G7&\"\"!\"\")F&F'" }}}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 24 "Ca cheSim(T3,8,1,1,true);" }}{PARA 6 "" 1 "" {TEXT -1 49 "Cache size = 8, Associativity = 1, Block size = 1" }}{PARA 6 "" 1 "" {TEXT -1 19 "Num ber of slots = 8" }}{PARA 6 "" 1 "" {TEXT -1 21 "1-th address = 0 -> 0 " }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 21 "2 -th address = 8 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 " " 1 "" {TEXT -1 21 "3-th address = 0 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 21 "4-th address = 8 -> 0" }} {PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 11 "" 1 "" {XPPMATH 20 "6#\" \"%" }}}{EXCHG {PARA 0 "> " 0 "" {MPLTEXT 1 0 24 "CacheSim(T3,4,2,1,tr ue);" }}{PARA 6 "" 1 "" {TEXT -1 49 "Cache size = 4, Associativity = 2 , Block size = 1" }}{PARA 6 "" 1 "" {TEXT -1 19 "Number of slots = 2" }}{PARA 6 "" 1 "" {TEXT -1 21 "1-th address = 0 -> 0" }}{PARA 6 "" 1 " " {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 21 "2-th address = 8 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 4 "miss" }}{PARA 6 "" 1 "" {TEXT -1 21 "3-th address = 0 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 6 " " 1 "" {TEXT -1 21 "4-th address = 8 -> 0" }}{PARA 6 "" 1 "" {TEXT -1 3 "hit" }}{PARA 11 "" 1 "" {XPPMATH 20 "6#\"\"#" }}}{EXCHG {PARA 0 "> \+ " 0 "" {MPLTEXT 1 0 0 "" }}}}{MARK "22 0 0" 0 }{VIEWOPTS 1 1 0 1 1 1803 1 1 1 1 }{PAGENUMBERS 0 1 2 33 1 1 }