# Cache Simulator
# Inputs:
#   addr : a list of addresses
#      C : Cache size
#      A : Associativity
#      B : Block size
#  TRACE : boolean flag.  If TRACE is true, each address in the trace is printed along
#          with a message indicating whether the cache access was a hit or not.
# Output:
#  misses : the number of cache misses that would occur using the specified cache design
#           on the given sequence of addresses.       

CacheSim := proc(addr,C,A,B,TRACE)
  local cache, slots, i, j, n, block, offset, index, found, rep, minclock, misses;
  cache := Cache(C,A,B);  slots := C/(A*B);  misses := 0;
  printf("Cache size = %d, Associativity = %d, Block size = %d\n",C,A,B);
  printf("Number of slots = %d\n",slots);
  n := nops(addr);
  for i from 1 to n do  
    block := floor(addr[i]/B);  offset := addr[i] mod B;
    index := block mod slots;  found := false;
    if TRACE then printf("%d-th address = %d -> %d\n",i,addr[i],index); fi;
    for j from 0 to A-1 do
      if block = cache[index,j][tag] and cache[index,j][clock] > 0 then
         found := true;  cache[index,j][clock] := i;  
         if TRACE then printf("hit\n"); fi;
      fi;
    od;
    if not found then
      if TRACE then printf("miss\n"); fi;
      misses := misses + 1; minclock := n+1;  
      for j from 0 to A-1 do       
        if cache[index,j][clock] < minclock then  
          minclock := cache[index,j][clock];  rep := j;
        fi;
      od;
      cache[index,rep][tag] := block;
      cache[index,rep][clock] := i;
    fi;
  od;
  return misses;
end;