Main Page

Announcements
(Section 501/701 Latest: June 20, 2009)
(Section 601 Latest: June 20, 2009)

Lectures

Project

Assignments &
Study Guides

Course
Guidelines

Programs

Resources

Syllabus

Grading Policy

ECEC 355 Computer Structures

Course Description: 

This course covers performance evaluation and benchmarking, pipelining, memory hierarchy, superscalar processors, multiprocessors, and interfacing processors and peripherals. See syllabus for more details.

Instructor
Section 501/701 - Bill Mongan - email: wmm24@cs.drexel.edu
Section 601- Bill Mongan - email: wmm24@cs.drexel.edu

 

Office hours
Bill - Tuesday 5-6pm on Main Campus (UC113), Monday/Wednesday 1-2pm at the BCC campus (BCC TEC 211A), and by appointment.
TA - Vinayak Honkote (vh32) - Monday 3-5pm on main campus.

Meeting Time
Section 501/701: T 6-8:50pm in CAT 268
Section 601: MW 11-12:50pm in BCC

Textbook

1. Required text: Patterson and Hennessy: Computer Organization and Design: The Hardware / Software Interface, 3rd Edition

 

Last edited: 01/04/2006 wmm24@cs.drexel.edu